The present invention discloses a method of manufacturing integrated circuit (“IC”) packages and, more particularly, to a method of manufacturing wafer-level packages for integrated circuits. Conventionally, IC packages are manufactured as wafers, each wafer containing many individual circuits, i.e., base wafers or dies. The wafer is fabricated and processed as a whole. After fabrication and processing, the wafer is cut, i.e., singulated, into a multiplicity of individual dies. Each base wafer or die is then encapsulated in a plastic or ceramic package or is fixedly and operationally attached to a ceramic cap.
IC base wafer fabrication is commonly referred to as the “front-end” process of IC fabrication. Packaging individual dies is commonly referred to as the “back-end” process of IC fabrication.
An IC base wafer can be fabricated relatively efficiently, because, as a rule, all dies on the wafer are fabricated concurrently, i.e., in parallel, such as by photolithographic processing. In photolithographic processing, each layer of the wafer is produced at one time, e.g., using a lithographic mask and/or a photo-resist. As a result, the time required to fabricate a wafer is largely independent of the number of dies on the wafer, but strongly dependent on the number of fabrication steps in the photolithographic process. In contrast, typically, after the dies are singulated, packaging or “back-end” processing is time consuming and expensive, because each die must be packaged individually, i.e., serially.
Dies include electrical leads, contact pads, and/or interconnects on one or more surfaces. The leads, contact pads, and/or interconnects are used to electrically-couple a completed IC die to, e.g., a printed-wire circuit board, other dies, and so forth. During “back-end” packaging, especially when a die is hermetically-sealed using a cap wafer, these interconnects are connected to associated leads, contact pads, and/or interconnects disposed on the front surface of the cap wafer. Through-wafer, electrical interconnects, or “vias”, are used conventionally to connect the interconnects on the front surface of the cap wafer to associated interconnects on the back surface of the cap wafer.
Conventional methods for providing through-wafer, electrical interconnects include the use of bonding wires, through-wafer etching of holes and/or interconnects, and/or etching of side-wall interconnects. Bonding wires provided on the front surface and/or on the back surface of an IC device are common. When enclosed or encapsulated, bonding wires work satisfactorily. However, when left exposed, especially in a harsh environment, bonding wires can interfere with the operation and/or cause the failure of the IC device. Wire bonding, however, yields larger sizes and, moreover, cannot be implemented by wafer-to-wafer.
Conventional through-wafer holes and/or interconnects offer better protection from exposure to a harsh environment. However, they also have several disadvantages. First, if the IC device is relatively thin, automated machines that make the through-wafer holes can only handle the relatively thin IC device with difficulty. Relatively thin through-wafer holes also can weaken the IC device during manufacture, which can result in batch rejections.
On the other hand, if the IC or MEMS device is relatively thick, the geometry of the through-wafer holes and/or interconnects, i.e., the aspect ratio of rise (thickness) to run (length or width), it is difficult to fill high aspect ratio hole with metal or other electrically-conductive materials. It also may require a relatively large footprint on the back surface of the IC device as a function of aspect ratio and thickness between the front and back surfaces, losing valuable surface area, which can affect through-wafer hole density.
Furthermore, high aspect ratio through-wafer holes require single-wafer, dry etching. Thus, etching of relatively thick IC or MEMS devices can be time consuming, which adds to manufacturing cost. Finally, through-wafer holes that are not located at the side-walls, can interfere with the hermetically-sealed cavity, which is undesirable.
Optical lithographical methods can provide three-dimensional, side-wall patterning. Advantageously, patterned, side-wall (or vertical-wall) interconnects provide points of contacts on both the front surface and the back surface of an IC device and are, relatively speaking, minimally intrusive. Indeed, typically, vertical-wall interconnects have a relatively large aspect ratio.
However, fabricating side-wall interconnects currently requires reflecting a collimating light off of one surface, e.g., a mirror, onto a surface, i.e., the side-wall, that is disposed orthogonally or substantially orthogonally to the direction of the collimating light. As it well known in optics, when light is reflected from a surface, surface scattering can be a problem. More particularly, the reflected collimating light experiences reduced or diminished light intensity and reduced or diminished resolution. As a result, fabrication of sloped side-wall interconnects, which is to say, relatively low aspect ratio side-wall interconnects, is impractical.
Therefore, it would be desirable to provide a method of manufacturing side-wall through-wafer holes or interconnects in an IC device that does not suffer from the same disadvantages of the prior art. More specifically, it would be desirable to provide a method of manufacturing side-wall interconnects that have relatively low aspect ratios, i.e., that are sloped. Furthermore, it would be desirable to provide side-wall through-wafer holes that do not affect or influence the cavity region of the IC device.